This invention relates to the switching of logic data signals, of the kind in which a change of logic state is represented by a change in potential of a predetermined magnitude.
The parallel interface standard for digital television equipment known as EBU 656 specifies Emitter Coupled Logic (ECL) signal levels, wherein a change of logic state is represented by a change between potentials of -0.8 v and -1.8 v. Therefore within digital television equipment it is often required to select between several of these 8 bit wide parallel data busses for reasons such as input and output signal selection.
Within the ECL logic family there are devices which will serve as data selectors but they have the following disadvantages:
(a) expense relative to other logic families such as TTL or CMOS PA1 (b) high power dissipation.
One solution to these problems is to level shift the incoming ECL data signals to TTL or CMOS levels within the equipment prior to processing the signal and to reconvert back to ECL level at the output. This can lead to implementation problems such as data to clock timing skews which leads to lack of noise immunity. For a simple system such as a 4 input to 2 output selector switch the cost of this solution is also high.